Requirements of modern computers increasingly burden the design of their memory modules due to increased output driver current and expected voltage slew rate.
During operation of the computer as each required circuit switches on, an output current is applied to its respective I/O pin or pad and, in turn, this current must flow from the driver power supply associated with the circuit being turned on. Consequently, where a large number of drivers switch simultaneously or at high frequency, a DC or AC shift in supply potential can occur which degrades the noise margins on the chip. This becomes more significant as power supply voltages decrease. Hence it is of importance to decrease the impedance of circuit modules.
In a paper entitled "Ground Bounce Control in CMOS Circuits" appearing in the "1988 IEEE International Solid State Circuits Conference Transactions", the problem of ground noise or bounce, due to the variation of the chip ground relative to the external ground, was discussed together with a proposed solution. This solution required having a control voltage source, tailored to the process creating the circuit, be created to regulate the charge/discharge rate of a series transistor in the output buffer and thereby equalize the delay, speed, rise/fall time and ground bounce of the CMOS output buffers thus requiring the faster element be slowed down. Further, this proposed solution is process dependent and cannot, for a number of practical purposes, be used in production.
U.S. Pat. No. 5,317,206 is directed to an attempt to stabilize voltage bounce within a circuit and does this by adding delay elements to the circuit. These delay elements, arranged to decrease the rising speed of the voltage at the circuit output, reduce the voltage noise but do so by sacrificing circuit speed.
Similarly U.S. Pat. No. 5,315,172 adds a pair of transistors serially connected between the voltage supply and ground with their common terminal connected to the circuit output so that, when either one of this serially connected pair is turned on, a slower rate of charge or discharge of the output occurs. This reduces the time rate of change of current through the circuit inductance and thereby reduces the voltage noise or bounce but again does do by sacrificing circuit speed.
U.S. Pat. No. 5,568,081 teaches the use of a variable slew rate control circuit for automatically adjusting the rate at which a node is driven to a voltage once again by sacrificing circuit speed.
As a practical solution, the semiconductor industry will only accept circuit changes that can be easily and inexpensively produced without sacrificing circuit speed or significantly impacting other circuit performance criteria. The present invention overcomes the above described problems without requiring additional circuit elements that impact circuit performance or speed.